Chiplet & 3D-IC

2.5D and 3D, through the standards

A photonic engine is not one die. It is a driver ASIC, a photonic die and a light source, stacked and bonded, with power and signals crossing between them. Lumicule carries that package through the real chiplet flow — ODSA-CDXML in, 3Dblox out — rather than treating packaging as a hand-off.

Open the workbench See the twelve stages

The stack

Three dies, one stack

Our PIC + EIC flip-chip design, as the platform's own chiplet visualiser reports it: three dies, a seven-layer metal stack, five signal groups. Take it apart.

Three dies, one stack, taken apart along one axis: the driver ASIC as its seven-layer metal stack, the photonic die flip-chip bonded above it, and the PCSEL light source on top, on a carrier board. Built with the vendored diagram-design skill (MIT) in our brand skin; the geometry is checked by the skill's own reprojection verifier.

The flow

Twelve stages, with the deliverable each one produces

Every stage produces a result you can inspect, and each one is a recorded job. Nothing here is a slide — this is the stage list the platform runs.

The chiplet flow, stage by stage
#	Stage	What it does	Deliverable
01	CDXML Parse	read the chiplet spec — mechanical, IO, thermal, electrical	Parsed chiplet definition
02	Boundary Manifest	die placement, rotation, flip-chip orientation	Boundary manifest
03	Assembly DRC	courtyard and interconnect checks against the assembly rules	Assembly DRC report
04	3Dblox Export	cross-die geometry for OpenROAD	3Dblox stack description
05	Package Thermal	multi-chiplet envelope with a liquid cold plate	Package thermal map
06	PDN IR-Drop	bump-array power delivery, temperature-aware	IR-drop report and drop map
07	Mech Stress	CTE mismatch and die-attach shear margins	Mechanical stress report
08	KGD Test Plan	known-good-die checklist per die role	Known-good-die plan
09	D2D Contract	the die-to-die interface both sides agree on	Die-to-die interface contract
10	Cross-Die STA	the delay budget across the die-to-die link	Cross-die delay budget
11	CPO Packaging	underfill, fibre and laser windows, assembly yield	Packaging process plan
12	ESG Carbon	carbon accounting over the package and its process	Carbon accounting report

Why the deliverables matter. A packaging flow that only produces a picture cannot be reviewed. Each stage above leaves a recorded result that a foundry, a test house or your own engineering team can read and disagree with.

Standards

What the flow speaks

Packaging is a supply-chain conversation. We read and write the formats the chain already uses, so a package does not have to be re-described to every party in it.

ODSA-CDXML

the open chiplet description format, read in at the start

3Dblox

the 3D-IC stack description, written out for the downstream flow

IHP-Open-ADK v0.2.0

assembly rule decks: ASM courtyard and IXN interconnect checks

UCIe

the die-to-die interface the D2D contract seeds from

IEEE P3537

the chiplet interface standard the contract also targets

UCLA 3D-IC benchmark suite

D0–D19 stack compositions, parsed from real .3dbx configs, used to test our own flow

What we design

Five domains, one package

PIC, EIC, FPGA, PCB and Chiplet designed in one project. This is what they become: one 2.5D artefact, layer by layer.

A 2.5D photonic package, taken apart along one axis: a carrier board, an interposer above it, and the three dies the platform designs together — the photonic die, the driver ASIC and the control FPGA. Five domains, one artefact. Built with the vendored diagram-design skill (MIT) in our brand skin; the geometry is checked by the skill's own reprojection verifier.

Calibrated honesty

Where 3D-IC stands with us

What is real today

The flow above runs, and its stages produce the artefacts listed. Assembly DRC is wired to the IHP-Open-ADK rule decks, 3Dblox export writes cross-die geometry, and the package thermal, IR-drop and mechanical-stress checks are the same tools the platform uses elsewhere.

What we do not claim

Cross-die timing is an architecture-level delay budget, not a signoff-grade static timing run. HBM appears in the package thermal envelope and in host packages — it is not our compute path, which holds weights as heater voltages in the driver ASIC. And we test our own flow against the UCLA 3D-IC benchmark suite rather than claiming a result on it.

Get started

Bring a package, not just a die

If your design has more than one die in it, the packaging is on the critical path. Tell us the stack and we will walk the flow with you.

Open the workbench Talk to Lumicule