Cell to packaged chip
Tap the figure to read it full-size
| Stage | What runs |
|---|---|
| Cells & PDK | Geometry, ports, measured S-parameters |
| Layout | Generated and edited against the DRC layer map |
| EM simulation | FEM · FDTD · EME on the real cross-section |
| DRC | Two independent engines, cross-checked |
| Tapeout | Layout, DRC/LVS record, provenance |
| Packaging | Assembly, clearance, package thermal |
Lumicule