The problemFive toolchains that do not talkvc-toolchainsAFTER TAPEOUTPICPhotonic layoutGDS · S-paramslayer mapEICDriver ASICSPICE · GDSdevice modelsFPGAFirmwareRTL · SDCbitstreamPCBCarrier boardschematic · netlistBOMCHIPLETChiplet assemblyCDXML · 3Dbloxbump mapLEGENDhanded over by handdiscovered after tapeoutFive domains, five toolchains, five formats, every handoff by hand — and the result that breaks another domain arrives after tapeout.5%of IC/ASIC projects hit first-silicon success in 2026 — 14.4% in 2024Siemens EDA · Wilson Research, Sept 202660–70%of engineering effort belongs in verificationSiemens EDA · Wilson Research, Sept 2025tens of $Ma mask set at an advanced node — one respin can take a product cycleSiemens EDA · Wilson Research, Sept 20252–3 yrsto design a leading chip, with hundreds of engineersSemiconductor Engineering, Aug 2024Re-spins surface late, when thermal, optical and electrical constraints collide.The failure surface moved to exactly where a photonic chip lives: firmware, thermal, packaging, cross-domain.Photonic design talent is scarce, and the tooling assumes you already have it.Lumicule